1. Technical Field
The present invention relates in general to a system and method for flushing instructions in the execution unit of a processor. More particularly, the present invention relates to a system and method for assigning a counter to each instruction in the execution unit in order to determine which instructions in the execution unit should be flushed in the event of an exception condition on the processor.
2. Description of the Related Art
Pipeline processing is a technique that provides simultaneous, or parallel, processing within a computer. It refers to overlapping operations by moving data or instructions into a conceptual pipe with all stages of the pipe executing simultaneously. For example, while one instruction is being executed, the computer may be decoding the next instruction. In vector processors, several steps in a floating point operation may be processed simultaneously.
The pipeline is divided into segments and each segment can execute its operation concurrently with the other segments. When a segment completes an operation, it passes the result to the next segment in the pipeline and fetches the next operation from the preceding segment. The final results of each instruction emerge at the end of the pipeline in rapid succession.
Out-of-order execution is a technique used to gain an edge in speed and performance. However, occasionally out of order execution may create a hazard. A hazard may cause the microprocessor to flush the fetched but incomplete instructions from the pipeline stages and to subsequently refill the pipe. However, as the number of pipeline stages in a processor increases, the overhead of flushing and refilling the pipe also increases leading to reduced performance.
Determining the retirement, or flush point, of a given instruction is a critical function in microprocessor design. For out-of-order designs, various approaches have been proposed. In an in-order design, an issue queue may allow certain instructions, for example from a floating point pipeline, to issue and execute in parallel with other instructions, such as fixed point instructions from a different pipeline. While using a plurality of pipelines allows greater throughput of instructions through the multiple pipelines, it also creates certain challenges when instruction flushes occur.
One challenge of using multiple pipelines in an in-order processor is that a mechanism is needed to keep track of the order that instructions were issued to the execution units that are running in parallel and may run independently of each other (such as the pipeline for floating point instructions and the pipeline for fixed point instructions). In other words, a mechanism is needed to allow the issue queue and pipeline of one execution unit to be decoupled from the various issue queues and pipelines of other execution units so that greater efficiency and throughput can be achieved while still maintaining a sense of order regarding an exception (flush) point in an in-order processor. A further challenge is that the mechanism used to keep track of the issue queues and execution pipelines with respect to each other, needs to be fast and efficient so that it does not degrade the overall speed and efficiency of the processor.
What is needed, therefore, is a system and method that tracks the order of instructions in one execution unit with respect to instructions in another execution unit without adding undue complexity that hampers system performance. One execution unit will become the reference point for other execution units that operate independently and may have issue queues that prevent simple synchronization between pipelines. Furthermore, what is needed is a system and method that allows for more complex flush operations, such as the ability to flush all instructions that are at least one instruction away from the exception point.